Dear dhaval
I convert my synthesized veriolg code into spice netlist but i have a problem.
Every Cell (subcircuit) has its own VDD and VSS net name,
Code:
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XU9 PA n9 X1[0] VDD_dummy47 VSS_dummy48 NAND2_X1
XU8 PA n8 X1[1] VDD_dummy49 VSS_dummy50 NAND2_X1
XU7 PA n7 X1[2] VDD_dummy51 VSS_dummy52 NAND2_X1
XU6 PA n6 X1[3] VDD_dummy53 VSS_dummy54 NAND2_X1
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I want all the cells VDD and VSS be connected to the global supply net.
What do you suggest?
Thanks in advance.
Oveis.