Is wait statement syntehsizable in VHDL?

[kalaiyarasan]

In VHDL whether wait statement is synthesizable or not...
if it is partially synthesizable in which kind of statement it is synthesisable

 

[vipinlal]

wait statement

In VHDL, wait statement is not synthesis able at all.The maximum you can do is create a counter and wait for the count value till it reaches a preset value.

--vipin
https://vhdlguru.blogspot.com/

 

[Maxwell077]

Re: wait statement

If you use it as a 'process', it's synthesizable.
For eq : wait until clk'event and clk = '1'...

 

[TrickyDicky]

wait statement

the following template for processes is also synthesisable:

process
begin
  wait until rising_edge(clk);
  .....
end process;

 

[anoop12]

Re: wait statement

It is not recommended coding practice to use wait statement for synthesis. use 'event attribute, that too for clock rising edge.

If you want to create a delay, then go for counter implementation with enable.