Is this verilog code synthesizable?

[nervecell_23]

Hi,

I want to capture the data that is available one clock cycle after the rising of a certain flag.

I experimented with the following code and it worked:

always@(posedge clk)
  begin
      if(flag == 1)begin
        @(posedge clk);
        $fwrite(file,"%d\n",data);
      end
    
  end

I find this very convenient because previously I have to create a new signal which equals to 'flag' with one clock cycle delay and then capture the data when the delayed signal is high.

I'm wondering if the above code is synthesizable and if it is the same thing as the conventional way of doing it in terms of the generated hardware after synthesis?

Thanks!

 

[star_golden]

Not synthesizable.
Probably you use $fwrite in testbench. So, why do you want to synthesize

 

[TrickyDicky]

what hardware do you expect $fwrite to synthesise to?

 

[nervecell_23]

what hardware do you expect $fwrite to synthesise to?

Sorry I didn't make it clear. I used above code for testbench. What I mean is if I can use the same coding style in synthesis after replacing '$fwrite' line with something else say 'a<=b;'.

- - - Updated - - -

Not synthesizable.
Probably you use $fwrite in testbench. So, why do you want to synthesize

Sorry I didn't make it clear. I used above code for testbench. What I mean is if I can use the same coding style in synthesis after replacing '$fwrite' line with something else say 'a<=b;'.

 

[TrickyDicky]

you cannot embed another timing statement inside an always block. In real hardware, it would be impossible to detect an edge at a clock edge.

 

[FvM]

Nested edge sensitive events are definitely not synthesizable.