is this solution right??

[aslijia]

i saw a question like this:
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Convert D-latch into divider by 2.
What is the max clock frequency the circuit can handle ?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS
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his solution is:
--------------------------------------------------------

Any system with clock should meet setup and hold time conditions.
Besides since there is a feedback from !Q to D, we should take care of
D input timing: the data on D input should not change while clock is high!
Otherwise the results are unpredictable.
To meet these conditions:

t_clock_high <= T_prop

t_clock_low >= T_setup

T_hold <= T_prop

For example if we take t_clock_high= t_clock_low = 6nS
Then clock period = 12nS,i.e max Freq = 80MHz
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but i think the clock period must longer than the total time of T_propagation + T_setup = 10ns + 6ns = 16 ns, but not 12ns as he advised.


regards
aslijia

 

[svicent]

I think your solution is OK with a D flip-flop and his solution is OK with a D-Latch.

 

[aslijia]

to svicent
yes, you are right. i can understand now. thanks very much.