Is this result reasonable?

[eruisi]

Design compiler reports the area is 117,000um2.
After P&R, the area measured is 67,000um2, only half of the DC's estimation!


Is this reasonable?

 

[cydi]

I think that there is some problem. Normally the difference is between 10 to 30% only. You may have to check the parameters again

 

[hgz]

Yes, please check it. Something is wrong

 

[sumit_techkgp]

There must be something very very wrong.Please check your P&R Script.
Sumit

 

[sameer_dlh25]

Hi eruisi,

Check your wire load model in DC. I am suspecting it is too pessimistic....

 

[leeenghan]

Hi,

My first guess is that the wire load model include the area for the routing wire.

My second guess is the area in .lib is not true area; it might be number of wire track or unit cell. In P&R maybe the area is taken from LEF.


Regards,
Eng Han

 

[shiv_emf]

Now which one of above is false ??
can DC report false area??
i wonder ..

n area of rounting wire ? exact length is unknown here !!!!!!!

 

[leeenghan]

Hi Shiv_emf

Not all ".lib" contain the true size of the cell (i.e. x by y). Some use placement track. So the area of an inverter can be 4 placement track but the true area can be 1.245um2.

Secondly, you are wrong to say that "exact length is unknow here". Doyou understand what exactly is wireload model? Wire load model will give C, R and even length. An area/unit length can be defined in the wireload model. This is not always the case in all wire load model, but is not uncommon.


Regards,
Eng Han