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Is this example from verilog-AMS LRM wrong?

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ruwan2

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Hi,

I dig deep trying to use an ADC example from verilog-AMS LRM. It has errors:


SMASH (release 6.3.0 of Dec 16 2014)
Control file: 'C:\Program Files (x86)\Dolphin\Solutions 2014 Q4\smash\examples\Verilog-Ams\PLL\testbench.pat'
COMMENT: Analyzing Verilog file C:\Program Files (x86)\Dolphin\Solutions 2014 Q4\smash\examples\Verilog-Ams\PLL\adc_LRM.vams
ERROR: only branch/analog net can be assigned in contribution statement
Generating module 'adc'


for the module:

Page 89/437:
module adc(in, clk, out);
parameter bits = 8, fullscale = 1.0, dly = 0, ttime = 10n;
input in, clk;
output [0:bits-1] out;
electrical in, clk;
electrical [0:bits-1] out;
real sample, thresh;
integer result[0:bits-1];
genvar i;
analog begin
@(cross(V(clk)-2.5, +1)) begin
sample = V(in);
thresh = fullscale/2.0;
for (i = bits - 1; i >= 0; i = i - 1) begin
if (sample > thresh) begin
result = 1.0;
sample = sample - thresh;
end
else begin
result = 0.0;
end
sample = 2.0*sample;
end
end
for (i = 0; i < bits; i = i + 1) begin
V(out) <+ transition(result, dly, ttime);
end
end
endmodule



In the example, " V(out) <+ transition(result, dly, ttime);", 'out' is not a branch. It is a port. Is LRM wrong or SMASH wrong for this problem?
 

beeflobill

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Although it's tempting to be snarky about the quality of code in the LRM and do nothing else, I resisted that temptation. I setup a quick simulation with Cadence's tool irun, and it compiled without any error.

Therefore, I think it is either a problem with SMASH itself or with something else in your design. I'd bet that it is something else in your design.

A random guess, can it possibly be that there is another source driving the output of this adc block? If not, maybe you could show what you have connected the block.
 

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