Is this circuit a Latch ?

[AdvaRes]

Hi members,

The first picture shows a transmission gate based latch.
I simulated the following circuit without the feeadback and it behaves like a latch. Is that really a latch, and what are its drawbacks compared to the first circuit ?

 

[keith1200rs]

Is that a Latch ?

The second circuit isn't really a latch, but I guess it could hold its state for a short period of time, like a sample & hold. It is really just a transmission gate.

Keith

 

[AdvaRes]

Re: Is that a Latch ?

Thank you keith1200rs.
Simulation showed that the second circuit can hold the value. Could you explain why?
Shoudn't be in unknown state since the input of the inverter become at the high impedance Z when e=0.

 

[keith1200rs]

Is that a Latch ?

It will hold its state because you will charge (or discharge) the gate capacitance of the output buffer [correction - inverter] and there is nothing to discharge it. It is like a sample and hold, but relying simply on the transistor gate capacitance to hold the voltage.

Keith

 

[AdvaRes]

Is that a Latch ?

Ok seems interresting.
Since it can behave like a latch for a short period of time, I think that It can be used instead Latch since I'll use it for the design of a very high speed circuit. So I can gain some transistors and some Watts.

Do you have an Idea keith1200rs, how to mesure this amount of time during which the circuit 2 can hold the data ?
Can I do that by simulation ?

 

[keith1200rs]

Is that a Latch ?

Leakage will discharge it. You could look in the process specification for the worst case gate leakage and add that to the output inverter and simulate it.

Watch out for changes in the output inverter input voltage due to charge injection when you turn the transmission gate off.

I see nothing wrong with using the idea as a latch as long as you are careful. DRAM works on the same principle.

Keith

 

[AdvaRes]

Is that a Latch ?

I understand now.
Thanks you so much keith1200rs !
Regards,
Advares.