Feb 8, 2006 #1 L leonken Full Member level 3 Joined Jun 12, 2004 Messages 169 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 1,437 I found a floating varactor in cmos technology from Razavi's paper in 1999. Is this floating varactor can be used as a floating forward biased diode in CMOS process without a latch-up problem? Thank you!
I found a floating varactor in cmos technology from Razavi's paper in 1999. Is this floating varactor can be used as a floating forward biased diode in CMOS process without a latch-up problem? Thank you!
Feb 10, 2006 #2 A alexbsb Newbie level 1 Joined Jan 16, 2006 Messages 0 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,280 Activity points 1,294 mybe is ok,but the doide is p+&n-well,not the p+&n+.
Feb 18, 2006 #3 9 993066935 Newbie level 4 Joined Jan 26, 2006 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,322 I think they use the n-well process as the epita-layer, so this P+ N+ may work.
Feb 19, 2006 #4 L leonken Full Member level 3 Joined Jun 12, 2004 Messages 169 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 1,437 993066935 said: I think they use the n-well process as the epita-layer, so this P+ N+ may work. Click to expand... Can you explain it more detail, or give me some documents? thank you!
993066935 said: I think they use the n-well process as the epita-layer, so this P+ N+ may work. Click to expand... Can you explain it more detail, or give me some documents? thank you!