is this a decent code of verilog to synthesize

[appu1985]

module out2(clk,j,lrate,w,y,xi,psw,g,w1);


input lrate;
input [7:0]j;
input [7:0]y ;
input [7:0] xi;
input [7:0] w ;
input [7:0]psw;
input clk;

wire  [15:0]d;
wire  [23:0]out;
wire  [23:0]temp;		 
wire  [23:0]temp1;
wire  [15:0]y2;
						
output [23:0]g;
output [23:0]w1;
 

	       assign  d = lrate * y;   
			 assign  out = d * xi;    
			 assign temp = out + w;  
			 assign y2 = w[j] * y[j] ;
          assign temp1 = psw + y2;
			
   		 assign g  = temp1 + psw;
		    assign w1 = temp - temp1;
			
endmodule

 

[nand_gates]

this is not a decent verilog code to synthesize. We are not clear what
you are trying to realize using this code? May be a digital filter!
But this is not the way to realize a digital filter in verilog. Multiplier
operation requires huge logic and ur making use of 4 multipliters.
Some better architecture is required. What kind of no. system ur using (unsigned int, int, fixed point, floting point ) is also important.

 

[funster]

you should add comments and use less multiplier.

the code's intent is not clear, and the gate counts will be huge.

furthermore, you should use meaningful name for signal.

module out2(clk,j,lrate,w,y,xi,psw,g,w1);


input lrate;
input [7:0]j;
input [7:0]y ;
input [7:0] xi;
input [7:0] w ;
input [7:0]psw;
input clk;

wire  [15:0]d;
wire  [23:0]out;
wire  [23:0]temp;		 
wire  [23:0]temp1;
wire  [15:0]y2;
						
output [23:0]g;
output [23:0]w1;
 

	       assign  d = lrate * y;   
			 assign  out = d * xi;    
			 assign temp = out + w;  
			 assign y2 = w[j] * y[j] ;
          assign temp1 = psw + y2;
			
   		 assign g  = temp1 + psw;
		    assign w1 = temp - temp1;
			
endmodule

 

[echo47]

Not so fast, guys! That module synthesizes very easily and with small area in a Spartan-3, for example.
However, I agree that the code looks highly suspicious, and probably doesn't do what the author intended.
For example, lrate, w[j], and y[j] are only one-bit wide, and clk is unused.

appu1985 - In another message you said you were using Xilinx ISE. What type of FPGA are you using?

 

[appu1985]

I am using Vertex 4 and besides. I have to use multipliers to implement this logic.
I want to use fixed point arithmatic pls help me in that.
Can u tell me if we can use Instantiations in if else.
i.e. on combinational logic be instantiated when some signal is there other when some other signal is there.

Added after 51 seconds:

if i want to pass multi bit wide data how can we pass them in modules

 

[echo47]

Virtex-4 has nice hardware multipliers.

Please clarify your question about instantiation. I'm not sure if you are referring to a compile-time decision, or a run-time decision. The word "instantiation" usually refers to compile-time, and signal-controlled decisions refer to run-time.

You are already passing 8-bit and 24-bit values through most of your I/O ports. However "lrate" is only single-bit, and that seems suspicious. If w and y are suppose to be register arrays (like RAMs), then you haven't defined them correctly. Also, Verilog doesn't allow passing a register array through a module port.

I haven't seen a good tutorial on fixed-point techniques. Maybe someone else can help you find one.

 

[appu1985]

okey... i mean instantiation can it be made in always block.
suppose i have

always@(m1)
begin
case(m1)
1://Instantiate one module
2://Instantiate other module
default
end

is this ok....to do or someother technique should beemployed

 

[echo47]

If I understand your question correctly, then no, you can't do that. "Instantiate" means to add some logic to your design. You can't use a run-time signal such as 'm1' to add/remove logic from your design.

One alternative - you could instantiate both modules, and then use 'm1' to control multiplexers that switch between the two sets of module signals.

Another alternative - you could design one big module that can perform both operations, and then pass 'm1' into the module to select the desired operation.

If 'm1' is a compile-time constant and not a run-time changing signal, then yes you can instantiate one of two modules depending on that constant. However, the syntax would be very different from what you've written. Search for "generate" in a Verilog 2001 manual.

 

[reyge]

Tell us what you want to do with your module and perhaps we can give more info...

about the fixed point arithmetic, i dont have a good tutorial about it but i learned it from this site and it was a good starting point.
http://www.ie.u-ryukyu.ac.jp/~wada/design05/spec_e.html
its in section 4.

about instantiation in an always block, i believe that cant be done.. what you can do is for every case, enable the module that you want to "instantiate" and disable all the others