library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port (
clk : in std_logic;
reset_n : in std_logic;
count : out std_logic_vector(7 downto 0));
end counter;
architecture behav of counter is
begin -- behav
counting: process (clk, reset_n)
variable count_tmp : std_logic_vector(7 downto 0);
begin -- process counting
if reset_n = '0' then -- asynchronous reset (active low)
count_tmp := (others => '0');
count <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
count_tmp := count_tmp + 1;
count <= count_tmp;
end if;
end process counting;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity tst is
end tst;
architecture tst_behave of tst is
component counter
port (
clk : in std_logic;
reset_n : in std_logic;
count : out std_logic_vector(7 downto 0));
end component;
signal count : std_logic_vector(7 downto 0);
signal clk : std_logic := '0';
signal reset_n : std_logic := '0';
signal count_reg : std_logic_vector(7 downto 0) := (others => '0');
begin -- tst_behave
clk <= transport not clk after 5 ns;
u1 : counter port map (
clk => clk,
reset_n => reset_n,
count => count);
process
begin
wait until rising_edge(clk);
count_reg <= count;
end process;
process
begin
wait for 24 ns;
reset_n <= '1';
wait for 1000 ns;
reset_n <= '0';
wait;
end process;
end tst_behave;