Is this a bug of ModelSim or a bug of my design

[presto]

modelsim delta delay problem

Hi, there,

I think this code can delay the 'wufifo_out' for one cycle.

    process
    begin
        wait until rising_edge(sys_clk);
        test <= wufifo_out;
    end process;

However, it's waveform goes as illustrated in the attachment.



NB. the 'wufifo_out' is changing at the rising edge of 'sys_clk' as well.

So what should I do if I want to delay the 'wufifo_out' for one cycle?

Many thanks

David

 

[nand_gates]

modelsim wait until

The result you got is clearly wrong for the code!

Which version of Modelsim are you using??? On which platform??
How you are generation the signal "wufifo_out" ???

I tried simple code given below. And it works fine for "count_reg" signal

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
  
  port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    count   : out std_logic_vector(7 downto 0));

end counter;

architecture behav of counter is

begin  -- behav
counting: process (clk, reset_n)
  variable count_tmp : std_logic_vector(7 downto 0);
begin  -- process counting
  if reset_n = '0' then                 -- asynchronous reset (active low)
    count_tmp := (others => '0'); 
    count <= (others => '0');
  elsif clk'event and clk = '1' then    -- rising clock edge
    count_tmp := count_tmp + 1; 
    count <= count_tmp;
  end if;
end process counting;
end behav;

library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity tst is
  
end tst;

architecture tst_behave of tst is
component counter
    port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    count   : out std_logic_vector(7 downto 0));
end component;
signal count : std_logic_vector(7 downto 0);
signal clk : std_logic := '0';
signal reset_n : std_logic := '0';
signal count_reg : std_logic_vector(7 downto 0) := (others => '0');
begin  -- tst_behave
  clk <= transport not clk after 5 ns;
  u1 : counter port map (
  clk     => clk,
  reset_n => reset_n,
  count   => count);

  process
  begin
    wait until rising_edge(clk);
    count_reg <= count;
  end process;
  process
  begin
    wait for 24 ns;
    reset_n <= '1';
    wait for 1000 ns;
    reset_n <= '0';
    wait;
  end process;
end tst_behave;

[/img]

 

[masai_mara]

modelsim edge bug

I have observed similar behaviour in modelsim and maybe has to do with the scheduling of events by the simulator and it sometimes disappears. so to ensure consistency it is advisable that you NOT give your input at exactly the same time that the clock edge occurs.

 

[zape]

modelsim delta cycle problem

I have experienced the same trouble once with ModelSim SE 5.8c (I think that was the version). I was informed that it was solved in the next release.

 

[haoboy]

modelsim bug 1000ns

i try it in 5.7f,but ok.

 

[presto]

modelsim clock assignment delta

Hi, there,

I've solved the problem.

The problem is that the 'wfifo_out' is driven by the rising edge a clock called 'wb_clk_i', and the relation between the 'wb_clk_i' and 'sys_clk' is

 sys_clk <= wb_clk_i;

So the ModelSim thinks that the 'sys_clk' is a little bit late than 'wb_clk_i', where I thought they would be the same at least in the synthesised and optimised netlist.

Anyway, when I use "wb_clk_i" instead of "sys_clk". The problem solved.

Thanks for your inputs.

 

[jitendra]

modelsim delta cycle

Hi,
Behaviour of modelsim is correct and its because of the coding style. As per the code of Pesto, modelsim will wait for rising edge of sys_clk and then schedule the assignment of signal test . So the value of signal wufifo_out will be assigned to signal test in next delta and not in the next cycle.
Simple way to achieve the goal of delaying this assignment by one cycle is use of intermediate signal. Please check the code below, it should serve the purpose.
=================================
process
begin
wait until rising_edge(sys_clk);
test_latched <= wufifo_out;
test <= test_latched;
end process;
=================================
Now in this code, assignment of test_latched and test will be scheduled on next delta after the rising edge of sys_clk. Signal test_latched will be assigned the value of wufifo_out and test will be assigned old value of test_latched. So in next cycle test will be assigned the value of test_latched i.e. value of wufifo_out in current cycle.

Regards,
Jitendra

 

[take_care00]

Hi presto,

Your solution is correct but your interpretation is not.

Because of the sys_clk <= wb_clk_i; assignement the VHDL standard requires that sys_clk change be scheduled to 1 delta cycle after a change in wb_clk_i signal. So, Modelsim is following the correct behavior.

Remember that in VHDL "<=" assignments are always scheduled to be processed in the next delta cycle while ":=" assignments are processed in the same delta cycle.

Take care.

 

[funzero]

similarly to block assignmnet or nonblock assignment in Verilog