Is there anyway to dump as waveform while simulation with systemverilog?

[u24c02]

Hi.
I'm trying to implement with systemverilog on uvm.
Is there anyway to dump while simulation with systemverilog?

 

[dave_59]

If you mean dumping the class based testbench object data in addition to the standard design signals, most tools support this with additional options. Read the User Manual for the tool you are simulating with.

 

[u24c02]

Thanks
I wondering about What if I use it with UVM then can I dump with them?l not just systemverilog?

As I know they are dynamic not stactic. So UVM can't do dump.

 

[dave_59]

I don't understand your question.

If you are using Questa, you can dump data generated by a UVM testbench into a waveform display.

 

[u24c02]

Got it thanks dave59