Depending on modeling philosophy (and particularly
important to things like RF switches and CMOS PA
antenna-matching) the metallization - gate poly
fringing capacitance may be separately, specially
treated (de-lumped from the gate-source, gate-
drain silicon-thinOx-gatePoly plate and fringe) in
the layout parasitic extraction and the SPICE /
Spectre model. This has to be kind of high-level-
architected to ensure that metal parasitics are not
"double billed" (whatever is within the device extent
as-recognized, vs what is outside, needs to be kept
consistent between modeling and post-extraction).