Is there any spice model file for SOI technology?

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Did you perhaps omit the Vgnd VS 0 0 statement?
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No. I simulated the code code that I mentioned in previous post. I really confused what is happening.

---------- Post added at 17:02 ---------- Previous post was at 16:31 ----------

I didn't omit that, I really donn't know what is happening as you see it acts like a buffer !!!!!!!!!!!!!!!
 

Exchange S & D !

ashkan_ed said:
I really don't know what is happening as you see it acts like a buffer !!!!!!!!!!!!!!
Click to expand...

For non-SOI MOSFETs, S and D nodes normally may be exchanged because of their inherent symmetry, but this may not be true for SOI MOSFETs, I guess. The (p. 67) shows the SOI-MOSFET Model Instance Syntax nodes order as

Mname <D node> <G node> <S node> <E node> [P node] ... - i.e. the 1st node should be the Drain.

... and the testX.sp examples from the BSIM_BSIMSOI4p1_Benchmarking directory respect this order - but not so Darsen Lu's inv_dc.sp example, even if the first (comment) line states the above given order:

ashkan_ed said:
Mx Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
* Modified by Darsen Lu 03/11/2009
Click to expand...

So I'd suggest to exchange the S & D in his example:
Code: 
MN0 Out Gate VS VS N1 W=10u L=0.18u NUMTERMS=5
MP0 Out Gate VD VD P1 W=20u L=0.18u NUMTERMS=5

... and try once more!
 
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I am puzzled that specifying NUMTERMS=5 and then only supplying 4 nodes would be expected to work. The example I posted works on my simulator. If I set NUMTERMS=5 and only provide 4 connections it stops working (I amm not surprised by that, although an error message would have been nice). If I then change NUMTERMS to 4 with 4 device terminals being used then it works again. Maybe it is a "quirk" of my simulator but it would seem that NUMTERMS being set to the actual number of terminals you are using would be a good idea.

Keith.
 

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