Is there any spice model file for SOI technology?

[rosaeidi]

Hi

Is there any spice model file for SOI technology?

Tx

 

[keith1200rs]

Yes.

I think you need to be more specific! Any particular process or manufacturer?

MOSFET level 57 models are SOI, I think.

Keith.

 

[dick_freebird]

No way. We've been getting by for 30+ years without anything
of the kind.

 

[animeshjn]

You can download them from Berkeley BSIMSOI website: **broken link removed**

 

[rosaeidi]

Dear Keith

Would you please explain more about "MOSFET level 57 models" for SOI?
I'm beginner in SOI design.

TX
Rosa

 

[keith1200rs]

If you get Hspice models from your foundry they will say "level=57" in the MOSFET model I think. Mind you, it seems the Berkeley ones are level 9. That is what tells the simulator that it is an SOI model. It is not uncommon to have to edit the level statement in the models if you use them on a Spice simulator other than the one it was intended for. I received level 57 models from a foundry and had to change it to level 9 for my simulator.

Keith.

 

[ashkan_ed]

I simulate an inverter with BSIMSOI model but the output is not like an inverter output, why my result is like this ?

 

[keith1200rs]

You will have to show your circuit and results to get a useful answer. Have you correctly connected all device terminals?

Keith

 

[ashkan_ed]

this is my code :

///////////////////////////////

Mx Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
* Modified by Darsen Lu 03/11/2009

.include ./nmos4p1.mod
.include ./pmos4p1.mod
.option TEMP=27C

Vpower VD 0 1.5
Vgnd VS 0 0

Vgate Gate VS PULSE(0v 1.5v 10ps 1ps 1ps 250ps 500ps)

MN0 VS Gate Out VS N1 W=10u L=0.18u
MP0 VD Gate Out VS P1 W=20u L=0.18u

.tran 0.01n 600ps
.print tran v(gate) v(out)

.END
//////////////////////////////////////////
please check it in your hspice simulator. this code is one of the examples that they present with their model .
I attached models in below.

thanks for your attention.

 

[keith1200rs]

I cannot immediately see why, but my suspicion is with the models. It may be an incompatibility with my simulator - it only supports the BSIM3 SOI - but even if I download the BSIM3 SOI models from Berkeley it doesn't work. However, if I replace the models with ones from an SOI process I have used before the simulation works.

I will try to track down where the error is but I have a few other things to do first.

Keith.

 

[erikl]

MP0 VD Gate Out VS P1 W=20u L=0.18u

Seems you connected the PMOS bulk to VS (GND) instead of VD .

 

[keith1200rs]

Yes, I noticed that as well, but correcting it didn't seem to make it work. Something else is wrong.

Keith.

 

[keith1200rs]

I am not sure if this will work with your simulator but give it a try:

MN0 VS Gate Out 0 VS N1 W=10u L=0.18u NUMTERMS=5
MP0 vd Gate out VD Vd P1 W=20u L=0.18u NUMTERMS=5

Keith.

 

[ashkan_ed]

[/COLOR]

Seems you connected the PMOS bulk to VS (GND) instead of VD .

thanks. you are right, but as I sad it is their example and with this change the out put didn't change much.

 

[keith1200rs]

Have you tried the change I suggested?

Keith

 

[ashkan_ed]

I am not sure if this will work with your simulator but give it a try:

MN0 VS Gate Out 0 VS N1 W=10u L=0.18u NUMTERMS=5
MP0 vd Gate out VD Vd P1 W=20u L=0.18u NUMTERMS=5

Keith.

I use Hspice 2008, could you tell me what simulator I should use to work with SOI ? which simulator do you use ? could you attach your model?
thanks again.

---------- Post added at 00:09 ---------- Previous post was at 00:08 ----------

Have you tried the change I suggested?

Keith

yes, I tried but it doesn't work

"
**error** (e:\hspice\bsim_bsimsoi4p1_benchmarking\inv_tr.sp:14) duplicate parameter being set or the number of element nodes is not within the range of 3-7.
**error** (e:\hspice\bsim_bsimsoi4p1_benchmarking\inv_tr.sp:14) difficulty in reading input
"


what do you suggest again ?!
sorry I didn't have permission to post for 3minutes :-(

thanks again again

 

[keith1200rs]

Hmm. I will look again ASAP. I use SIMetrix. I couldn't get your circuit to work with the Berkeley models but that change fixed it.

Keith

 

[erikl]

MN0 VS Gate Out 0 [COLOR="red"]VS[/COLOR] N1 W=10u L=0.18u NUMTERMS=5
MP0 vd Gate out VD [COLOR="red"]Vd[/COLOR] P1 W=20u L=0.18u NUMTERMS=5

**error** (e:\hspice\bsim_bsimsoi4p1_benchmarking\inv_tr.sp:14) duplicate parameter being set or the number of element nodes is not within the range of 3-7.

I guess the above red marked nodes are dispensable. Try:

MN0 VS Gate Out 0  N1 W=10u L=0.18u NUMTERMS=5
MP0 VD Gate Out VD P1 W=20u L=0.18u NUMTERMS=5

 

[ashkan_ed]

I guess the above red marked nodes are dispensable. Try:

MN0 VS Gate Out 0  N1 W=10u L=0.18u NUMTERMS=5
MP0 VD Gate Out VD P1 W=20u L=0.18u NUMTERMS=5

I attached the output with your correction. Is the SOI model works different ?

 

[erikl]

It looks like your VS node is floating w.r.t. to 0 (=GND)
Did you perhaps omit the Vgnd VS 0 0 statement?