Re: ASIC Physical Design
Yes.
Your noise margin (for a fully settled output) is the
distance from rail voltage to threshold voltage. At rails
come together (I*R applies to both vdd and vss) the
distance must shrink. And that's just for the simple
static case.
Now consider a case where a gate at the worst "sagged"
point of the core, tries to drive another gate that's well
supplied (say, right up near the periphery bussing). The
core gate will have a vss potential higher and a vdd
potential lower than the peripheral gate, so the offset
subtracts from static noise margin and also gives sub-par gate
drive levels to the receiving gate. This can cause timing
to push out, possibly making logic fail for causes that
are not comprehended by static timing analysis.
Then there's that the I*R drop is not at all static, and things
like simultaneous switching can bounce the rails and signals
driven from them, big time - not just I*R, but L*dI/dt on
top of that. With about 1nH/mm, and chip sizes well above
10mm, and tens of pS risetimes, that's some ugly arithmetic.
Then think about hundreds or thousands of registers flipping
on "special occasions", cranking their output through high
drive (hence high shoot-through) buffers and millimeters
of wireload apiece....