Probably because early designs started out with positive edge sensitivity and for compatibility reasons, people continued to design positive edge devices and circuits. Maybe it made more sense to do this because people were also using active high logic.
Also I would add that it used to be that way. Now it is not uncommon to find negative edge triggered systems or subsystems.
Actually, after looking at the implementation of simple sequential circuits, I see that the clock pulse goes into a NAND gate first. So maybe this is why, because NAND in CMOS is cheap and common.