Is there any reason that designs adopt Clock Positive Edge??

[khaila]

Generally each design that I meet consider the the clock at its positive edge only. While it is not considering it at Negative edge except special cases.

My question is Why Positive Edge and not Negative Edge???

 

[gliss]

Probably because early designs started out with positive edge sensitivity and for compatibility reasons, people continued to design positive edge devices and circuits. Maybe it made more sense to do this because people were also using active high logic.
Also I would add that it used to be that way. Now it is not uncommon to find negative edge triggered systems or subsystems.
Actually, after looking at the implementation of simple sequential circuits, I see that the clock pulse goes into a NAND gate first. So maybe this is why, because NAND in CMOS is cheap and common.

 

[avimit]

Re: Is there any reason that designs adopt Clock Positive Ed

Hi,
There isn't any reason behind +ive edge use. I guess its the same as adopting +ive logic and not -ive logic.
Also once ppl started using +ive edge, then for the sake of integration, the other designs were required to follow the same.
But some designs do use both +ive and -ive edge, to increase the throughput of the design. An DDR SDRAM and its controller is an example where both +ive and -ive edges are used.
Kr,
Avi
http://www.vlsiip.com

 

[darylz]

because of the architecture of FlipFlop