Is there a chip which includes a D FlipFlop and also a DELAYED Clock?

[andre_luis]

Sure, I´m starting to conclude that what began presumably simple to synthesize, now will require a lot of components.


+++

 

[Venkadesh_M]

Hi this can be done by SR flip flops and using only S lines because there is no state for reset...

 

[Lironsh]

Kerim, Sure. The ICs i use are:
- Quad DFF : SN74LS175N
- Six Inverters: CD4069UBE (every two inverters in series are connected for non-inverting and to get my delay)
- 100 Ohm Resistors

These are the exact ICs. The thing is that i tried it out and it works perfectly, so i guessed i could keep this configuration to achieve my goal, unless one of you think it's NOT a right configuration in Electronics, based on your professional opinion and from your experience.
You can try it out yourself.

FvM - it has to be non-inverting configuration, a delay only. thanks for your reply.

Just want to mention the goal again, which is to eliminate the buffer chip and have only one chip to include the delay. i'm trying to save room on the board so a replacement with other components won't give me any advantage. depending on their size.

Andre, you're right regarding the diodes, following what you're saying, i can replace the Buffer IC within 3 diodes (to prevent the high signal to other 'D' inputs and keep all clocks rising at the same time). this is good because 3 diodes is "cheaper" on the board (saves space, pins...). i will try it out. But now i still need a small delay to the DFF Clock in order to have my Q high the same time when D is set up (button pressed). if you give me the right chip for that, problem will be solved.

 

[KerimF]

I see. The clock-pin current of the LS175 (outwards) and the high level current of one CMOS output work together to raise the voltage of the two low-state CMOS outputs, up to Vih of the clock.
The right chip is a mini MCU with internal oscillator

 

[Venkadesh_M]

Try this,

If necessary add a pull down resistor at E0

 

[Ratch]

Lironsh,

Is there a chip which includes a D FlipFlop and also a DELAYED Clock?

I don't understand what you want. The very definition of a D-FF is that its output has its input delayed by one clock cycle. If you don't want a delay, then just connect your input directly without any FF.

Ratch

 

[Lironsh]

Venkadesh - Thanks for the tip, i will test the 4042 chip asap and see if it gives right solution (with the right polarity).

Ratch, I am actually not looking for a D-FF, i'm looking for a different chip that can meet my requirement to have the D state on the Q with the same pulse ("pulse=one time button pressed" in my application) and not delayed by one clock. eventually i want it to act as a switcher to pick up one output (without a MUX) and KEEP the output ON by every button press, and turn off the other outputs.