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Is the transport delay model in VHDL a synthesizable construct?

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shiva

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is the transport delay model in vhdl is a synthesizable construct?
 

Elephantus

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Re: synthesis_vhdl

I am not sure any delay model is a synthesizable construct as delays depend on target technology for synthesis - delays are usually used for modelling real-world circuitry in testbenches.
 

keano

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synthesis_vhdl

nope, delays aren't synthesizable
 

barkha

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Re: synthesis_vhdl

No delays are not synthesisable. They are generally used in test benches to replicate the actual hardware delays in the device and check the performance and functionality opf your logic.
 

sameer_dlh25

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Re: synthesis_vhdl

No any of the delay models is not synthesizable.
On actual hardware it is very difficult to meet a requirement of exact delay.
i.e. when you give after 2 ns clause it is very difficult to make a component with delay exactly of 2 ns.
:cry:
 

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