system verilog is an extesion of verilog, whatever u had in verilog 2001, its there in SV. Its a HDVL and can be used for RTL design and verification. for verification many features have been added which are mostly ripped from vera. some additional features have been implemented for design (and verification too) like modports.
Aha, this is a rather big question. I recommend you read the disussion about the comparision of verilog&vhdl&systemverilog first. Although this paper will not tell all that you expect, it at least illustrates some hot points you care about.
For this question, there's a paper that really describes the application field of C++/SystemC/SystemVerilog/Verilog or VHDL; unfortunately i cannot find this paper this time. However i'll paste it in the future time. Generally speaking, this paper demonstrates that Systemverilog will be best suitable in the field of constructing the testbench and some basic system modeling. SystemC(or C++) is very good for system modeling and algorithm anaysis. and Verilog and Vhdl etc. HDL are still best for describing the RTL or netlist .
Okay, Now the titile for this paper is "Designers May Find C++ to their Link", and you can google it.