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Is SystemVerilog different from Verilog?

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vishwa

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What is difference between SystemVerilog and Verilog.

What are the applications of SystemVerilog?
 

vivek

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system verilog is an extesion of verilog, whatever u had in verilog 2001, its there in SV. Its a HDVL and can be used for RTL design and verification. for verification many features have been added which are mostly ripped from vera. some additional features have been implemented for design (and verification too) like modports.
 

gliss

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Does SystemVerilog add many other features for synthesis besides modports?
 

horzonbluz

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You can read some paper of synopsys about systemverilog synthesis.
Then you can learn it.
 

spauls

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system verilog is a mixture of VHDL , vera and Verilog it is a HDVL ( Hardware design and verification language)
 

eda_ak

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Not exactly.

Verilog is a sub-set of SystemVerilog.

SystemVerilog = Verilog95 + Verilog2001+ lots of new stuff (see below)

New stuff = Powerful testbench features (based on C++ like inheritance, polymorphism etc) + ABV (Assertion Based Verification) language

ABV (IEEE 1800) is based on Vera + ??Spec (Intel's verification language - Intel donated this to SystemVerilog) + other verification stuff

Also you have 2 versions of SystemVerilog:

SystemVerilog 3.0 - Mainly has features for modeling (designing)
SystemVerilog 3.1 - Has mainly verification enhancements + modeling features

Hope this helps.

... still learning
 

Thomson

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vishwa said:
What is difference between SystemVerilog and Verilog.
Aha, this is a rather big question. I recommend you read the disussion about the comparision of verilog&vhdl&systemverilog first. Although this paper will not tell all that you expect, it at least illustrates some hot points you care about.


vishwa said:
What are the applications of SystemVerilog?
For this question, there's a paper that really describes the application field of C++/SystemC/SystemVerilog/Verilog or VHDL; unfortunately i cannot find this paper this time. However i'll paste it in the future time. Generally speaking, this paper demonstrates that Systemverilog will be best suitable in the field of constructing the testbench and some basic system modeling. SystemC(or C++) is very good for system modeling and algorithm anaysis. and Verilog and Vhdl etc. HDL are still best for describing the RTL or netlist .

Okay, Now the titile for this paper is "Designers May Find C++ to their Link", and you can google it.

BR,
Thomson
 

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