Is it possible to tie two bidirectional pins to each other?

[Soda]

Hey,

I'm working with a project where I need to do a simple voltage level shifting between mcu databus and a pheripheral. My question is: Is it possible to tie two bidirectional pins to each other? I'm using Lattice's MachXO.

I've tried this:

BIDIR_DATA1 <= BIDIR_DATA2 when (RW = '0') else (others => 'Z');
BIDIR_DATA2 <= BIDIR_DATA1 when (RW = '1') else (others => 'Z');

When I simulate my code with modelsim, output of the busses are 'Z's.

I'll appreciate any help! VHDL and CPLD/FPGAs are quite new "play ground" for me.

 

[master_picengineer]

Re: Bidirectional I/O

Please give more details

BIDIR_DATA1 <= BIDIR_DATA2 when (RW = '0') else (others => 'Z');
BIDIR_DATA2 <= BIDIR_DATA1 when (RW = '1') else (others => 'Z');

This mean BIDIR_DATA1 = BIDIR_DATA2 always. And With initial value='Z'.

 

[Iouri]

Bidirectional I/O

you right, do not forget to add pull up resistors, on actual pins, also in the model sim test bench add bidir_data1 <= 'H'; to simulate pull up resistors

 

[Soda]

Re: Bidirectional I/O

Thanks for the quick replies!

Here is the code, I've done so far:

library ieee;
use ieee.std_logic_1164.all;

entity block is
port(
BIDIR_DATA1: inout std_logic_vector (15 downto 0); --data signals
BIDIR_DATA2: inout std_logic_vector (15 downto 0);
RW: in std_logic);
end;

architecture makki of block is
begin

BIDIR_DATA1 <= BIDIR_DATA2 when (RW = '0') else (others => 'Z');
BIDIR_DATA2 <= BIDIR_DATA1 when (RW = '1') else (others => 'Z');

end makki;
end;

So, my idea is, that I have a cpld-ic between mcu and a pheripheral for voltage level shifting. I've connected different voltage supplies to the cpld's banks. Code doesn't need to do anything else but the level shifting.....Later on, I'll add more logic in to the circuit.


I simulated this with a testbench where I have those pull ups but I got a result where BIDIR_DATA1 <= BIDIR_DATA2 is ok, but BIDIR_DATA2 <= BIDIR_DATA1 is not. (some of the datas in BIDIR2 are 'X's).

By the way, I tried to put those sentences (bidir_data1 <= bidir_data2 etc..) inside the proces, but simulator gave me a fault: Illegal sequential statement.

Another question came my mind. If I'd like to connect some SDIO interface pheripheral to my mcu, for example WLAN module, I won't know when the data is going from mcu or to mcu. There is no any RW or enable signals available and all signals (execpt clock) are bidirectionals. Is that kind of connection possible to do with MachXO and VHDL?