Is it possible to synthesize?

[elektrom]

Is it possible to synthesize the post-place & route netlist? Any way to do that? Is it secure to send vhdl/verilog timing model to customer for evaluation propose?

 

[masai_mara]

Is it possible to synthesize the post-place & route netlist? Any way to do that? Is it secure to send vhdl/verilog timing model to customer for evaluation propose?

ofcourse it is possible and would be a very risky venture. But I think there are some packages out there which scramble the netlist in an undecipherable way, which disables any synthesis attempts and are safe to part with.
search for them on google.

rgds.

 

[Renjith]

Is it possible to synthesize the post-place & route netlist? Any way to do that?

hi Elecktrom,
Can u plz mention the purpose for Synthesising a Post-P&R design?

 

[elektrom]

Hi Renjith,
In case that someone want to stole your design and use it illegal way.
Rdgs,
Elektrom

 

[haoboy]

why do u want to do it?

 

[sarath51]

Is this regarding FPGA or ASIC Flow ? and how it is usefull

 

[hercules007]

Is this regarding FPGA or ASIC Flow ? and how it is usefull

I think it is FPGA flow!
BTW, in ASIC design, the netlist after post P&R with physical tools can be resynthesized ? I have not done this operation before!

 

[bibo1978]

I believe that you can send WLF files but even though you still are at risk, so usually you may take a snap shots "JPEG" of your testbench "simulation" results,
I believe there is another way that use some cryptographic technique so that no inverse engineering can be done but I dunno this way, so can any one help "links at least"

No done yet folks