Besides the said 50 MHz clock speed,, your posts are missing all informations to determine if your intention may work in this case, e.g. number of IO lines, number of supply rails, required respectively intended supply bypassing. Also PCB density plays an important role. I guess limiting the design to a dual layer board (which is apparently meaned with one layer PCB, if I understand your post right) also implies very basic density, e.g. 6 mils/150 u structure size. In this technology, you have even problems to route a single trace between 1 mm grid balls or vias.
Personally, I have used 484 pin BGA at minimal 4 layer boards, but it was only possible due to a rather sparse pin utilization. Under normal conditions, 6 layers and 4 mils/100 u structure size is minimum for 484 pin BGA (with 1 mm ball grid).