Hello,
I have implemented a design targeting a Virtex-5 FPGA and I use ISE 14.7. I am using ChipScope Pro Analyzer (ILA) to capture my signals in real world and my trigger/clock sampling frequency is 50 MHz. It means that ChipScope will sample by the speed of 50MHz. Now my question is that can I insert and watch a clk in my system that is around 400MHz? I did some trials and it seems that we cannot insert any clock signal in ChipScope for watching !!! Is it true??
Any kind help is cordially appreciated in advance !
Regards,