Ashish Agrawal
Member level 3
Hi,
Is it possible to complete one AXI 3 write transaction in just one clock cycle?
Provided This transaction has only one beat to write. And AWREADY, WREADY and BREADY are by default HIGH.
Lets say master sends the address and data in the same cycle (AWVALID, WVALID and WLAST in same cycle). Can a Slave send BRESP in the same cycle by asserting BVALID ?
Is this the protocol violation to have AWVALID and BVALID asserted in the same cycle?
Thanks,
Ashish
Is it possible to complete one AXI 3 write transaction in just one clock cycle?
Provided This transaction has only one beat to write. And AWREADY, WREADY and BREADY are by default HIGH.
Lets say master sends the address and data in the same cycle (AWVALID, WVALID and WLAST in same cycle). Can a Slave send BRESP in the same cycle by asserting BVALID ?
Is this the protocol violation to have AWVALID and BVALID asserted in the same cycle?
Thanks,
Ashish