Is it part of a code synthesizable?

[appu1985]

module out2(clk,j,w,y,xi,psw,w2);

parameter lrate= 0.1;

input [7:0]j;
input [12:0]y ;
input [7:0] xi;
input [4:0] w ;
input [4:0]psw;
input clk;

reg  [12:0]d;
reg  [20:0]out;
reg  [20:0]temp;		 
reg  [20:0]temp1;
reg  [15:0]y2;
reg [20:0]w1; 						

output [20:0]w2;
wire [20:0]w2;
 
				always @(posedge clk)
				begin
				 d <= lrate * y;   
			    out <= d * xi;    
			    temp <= out + w;  
			    y2 <= w[j] * y[j] ;
             temp1 <= psw + y2;
		       w1 = temp - temp1;
				 end
				 assign w2 = w1;
				
endmodule

 

[kishore2k4]

Re: Is it synthesizable

If it compiled in the first place without any errors even then it will not be synthesizable as you declared lrate parameter as a real value.

 

[appu1985]

Re: Is it synthesizable

Besides the parameter thing is everything else ok.

 

[kishore2k4]

Re: Is it synthesizable

If it compiled in the first place without any errors even then it will not be synthesizable as you declared lrate parameter as a real value.

Well for starters I only tested the code by changing the parameter to a integer value. I've no idea what your code does but its synthesizable but whether it is done as you intended or need requires some simulating/testing on your part.