is it necessary to run post_layout simulation for tape-out?

[ls000rhb]

i design a ASIC which is a full digital circuit.0.35um,80MHZ.After P&R using Apollo,the extracted sdf is annotated to the post_layout gate_level netlist. THE gate level simulation verify the function of the chip is right .is it necessary to run post_layout simulation for tape-out?

 

[billjoy]

of course

 

[SkyHigh]

Re: is it necessary to run post_layout simulation for tape-o

ls000rhb,

It's not just necessary. It is a must to perform post-layout simulation because you need to know if the actual design in a fabricated die will work. If your post-layout simulation fail, your actual design in a fabricated die will fail too. Post-layout simulation is so accurate that if it passes, your actual design in a fabricated die is guaranteed 95% to pass. 5% of failure is to due to process variation.

 

[tarkyss]

of course, the timing of post_layout may be varied with pre_layout

 

[hohoa]

for sure, if post layout can not find some system level design problem. it will find whether layout parasitic will kill some of your blocks.

 

[ls000rhb]

Re: is it necessary to run post_layout simulation for tape-o

to:billjoy SkyHigh tarkyss hohoa

thanks !but can you give me some detailed manual for Star_RCXT?

 

[AlexWan]

It's not just necessary for single clock design. STA and Formal tools will help you finish the functional and timing checking.

For SOC, there are many clock domain. So post-simulation is important. Now formal tool only compare the function between RTL and netlist. STA tool only analyze the timing of single clock domain. Verificaiton engineers have to do some post-simulation for verifying the sync logics.

Certainly, if you have enough time, you should do the post-simullation for each design.

 

[SkyHigh]

Re: is it necessary to run post_layout simulation for tape-o

ls000rhb,

Here's the link to download STAR_RCXT extraction tool from Synopsys:

**broken link removed**

 

[Yun Lin]

Sure. the timing checking is very important after the PR even you may think your design margin can cover it.

 

[brianhe]

Re: is it necessary to run post_layout simulation for tape-o

For rtl level simulation, we should run sim and pass all the tests, which is called regression.
But gate level simulation, we may not run all the test, because of time. We just select some classical test to run
So for timing, we depend more on STA or HW validation