stevepre said:Short answer is YES.
STA could be wrong if you set any constraints incorrectly. You need to run some gatesim to at least confirm it.
It's like your zero-delay gatesim to verify the funtionality even though your formal verification passes because some contraints when you do the formal verification might be wrong.
albred said:The post layout simulation is one part of IC design flow, while the function verification has been done by pre-layout simulation.
If the design has pass pre-layout simulation and post-layout STA, is it necessary to do post layout simulation for the design?
What's the issues that can't be detected by STA? What's the limitation of STA?
It's said that STA can't check the asynchronous timing?
albred said:The post layout simulation is one part of IC design flow, while the function verification has been done by pre-layout simulation.
If the design has pass pre-layout simulation and post-layout STA, is it necessary to do post layout simulation for the design?
What's the issues that can't be detected by STA? What's the limitation of STA?
It's said that STA can't check the asynchronous timing?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?