Is it all right to assign the port signals in instatiation?

[yinni]

I find in a reference design that one of the port signal 'reset' is assigned '0' directly in the port map part. I wonder if it is right to do so. What is the results in hardware? Thank you!

 

[dBUGGER]

Hi,
The synthesis tool will connect that to ground and give you a warning of reset Struck at ground. It may optimize away some of the logic also.

Best Regards,

 

[vardan]

Re: Is it all right to assign the port signals in instatiati

I find in a reference design that one of the port signal 'reset' is assigned '0' directly in the port map part. I wonder if it is right to do so. What is the results in hardware? Thank you!

Hi yinni,
As a result reset signal will always have 1'b0 value, i.e. it is hardwired to Gnd. I guess you meant Verilog module instantiation. You can use any valid expression in port assignment . For example,

module1 U_module1(
.rst(1'b0),
.en(sig1 & sig2),
.in({data1, data2}), // concatenation of data1 and data2 signals
.out() // out is not used
);

 

[tkbits]

Re: Is it all right to assign the port signals in instatiati

There is nothing wrong with setting an input directly with 0. All inputs must be connected to some signal. 0 is simply a signal which is always 0. Leaving an input open does not cause the input to be "ignored".