Is data loss captured by STA tools?

[Ashish Agrawal]

Hi,

If capture clock is divided clock of launch clock and data is changing on every launch clock, then every single change in data will not be captured (because its a divided clock).
In this case, will STA tool report a violation for data loss?
Is this a setup/hold violation? (Well I don't think it is a setup/hold violation because data is not changing near to active clock edge)


Thanks in advance.

 

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STA doesn't check the functionality of a design. It verifies the design against a set of timing constraints.

In your case it would analyze timing from the nearest launch edge to the rising edge of the divided clock, i.e. the period of the launch clock +/- the clock skeew between the two clocks.

 

[Ashish Agrawal]

STA doesn't check the functionality of a design. It verifies the design against a set of timing constraints.

In your case it would analyze timing from the nearest launch edge to the rising edge of the divided clock, i.e. the period of the launch clock +/- the clock skeew between the two clocks.

Is there no setup/hold violation as data has been changed before getting captured ?

 

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STA only verifies the timing of the design against the constraints, it doesn't generate the design and determine the path delays. So it can only report there are setup/hold violations. The existence or lack of setup/hold violations is determined by the synthesis, clock tree synthesis, placement, and routing of the design.

I think you are confused as to what STA is for.