Is clock sampling (OSR) externally controllable for SDM?

[sehun1119]

osr clock

Hi, all,

is clock sampling with over sampling rate externally controllable for sigma delta ADCs?

I am working in a testing and reliability group in mixed-signal area.

I am trying to use the same input signal (ie. sinusoidal signal) to the sigma delta model with different over sampling rates. I wonder that one sigmal delta modulator can have different over sampling rate.

Thank you in advance,

 

[A.Anand Srinivasan]

the oversampling rate depends on the capacitor used for holding the input signal to be sampled.... i think there is a possibility of changing the oversampling rate by using a external capacitor...

 

[sehun1119]

Thanks for your reply, A.Anand Srinivasan.

Is that capacitor in the integrator?

From "possibility" using an external capacitor you said, does no current sigma delta modulator have a controllability on over sampling rate so far?

Thanks

 

[A.Anand Srinivasan]

ya it is part of the integrator only.... i've not seen SDM like that so far but maybe it is available,.... one main problem would be that since these SDMs are being designed using fixed response time and other things the usage of external cap would cause nonlinearity....