Is block Vhdl statement Synthesizable?

[savour]

vhdl block statement

I want to use the "block" vhdl statement for structural modularity.
From your experience with synthesizers (design compiler, sinplify, quartus, xilinx ise) is that a valid vhdl statement for synthesis?

Also can "block" statement easily converted to verilog with the vhdl to verilog conversion tools?

Many thanks,
savour

 

[standardon]

block vhdl

block statement can also be synthesis,but if you don't know how to use it ,maybe the ender of synthesizers is not what you want!