io delays in synplify premier

[pawangupta]

Hi,

I have couple of doubts in timing constraints..& i am new to Synthesis...
Plz help me to understand this...

1. What is the significance of input/outputs delays in timing constraints (.sdc) in synplify??

2. How we can calculate input/outputs delays of a port of my design top in terms of ns??

Thanks

 

[randyest]

set_input_delay specifies the input arrival time of a signal in relation to the clock. It is used at the input ports, to specify the time it takes for the data to be stable after the clock edge. The timing specification of the design usually contains this information, as the setup/hold time requirements for input signals. set_output_delay specifies the output signal time required relative to the clock.

input delay subtracts from your available clock period for paths from input pins to first register. output delay subtracts from your available clock period for paths from last register to output pin.

You calculate these from the specification of the rest of the system.

try this guide:
https://www.cadence.com/community/b...ruction-what-s-it-s-function-part-2-of-4.aspx

 

[pawangupta]

Thanks randyest....I will go through the attached link...if still not clear to me i will get back to you...

 

[pawangupta]

Hi,

Say for example, my design in FPGA is running at 100 MHz feq (period =10ns). My design top is having AXI related inputs & outputs which should work on pro clock. Definitely my chip has to be connected to outside chip on a board.

Plz go though attached diagram...



Case: I am not aware of i/o delay parameters of those 2 chips. Normally input & output delay of my chip will be definitely less than my clock period.But how much i don't know...How to judge accurate i/o delays for my chip without knowing i/o delays of the supposed to be connected chips???

 

[randyest]

Does your FPGA and the other two chips it talks to use the same clock?

Maybe p.13 of this will help:
**broken link removed**

 

[pawangupta]

Hi randyest,

Thanks for the link & your reply...
I know my design in FPGA works on 2 clocks derived by DCM in my FPGA. You
had given more possibilities:

Case 1: If Chip 1 & 2 works on different clock other than my FPGA....
Case 2: Chip 1 & 2 clock same as my FPGA...

Whether as an IP provider i need to worry about other chips input & output delays??
Moreover my design is bounded by DCM & IOs of my FPGA...really i should know the I/O delays of other chips?? If no how can i constrain I?O delays of my design in terms of ns??

 

[randyest]

Sorry, what's DCM?

Yes, I think you're understanding it now. If you don't know anything about the other chips you need to talk to, then to make your design maximally robust you can set input and output delays to be your clock period minus IO buffer delay and a little margin for wire from IO to register. This will give maximum slack to the other chips.

This is generally a pretty reasonable practice -- to basically force the tool to register all inputs and outputs. Unless you have special latency concerns, there's probably no big drawback.

Good luck!

 

[fpga1]

Hi!
Thanks for your comments!
I was trying to understand the document you recommended and have a question. concerning the example of page 13:
Example 1
If the delay from the clock port of cell L1 to the input IN1 (minus the load-dependent delay of
the driving cell) is 4.5, the set_input_delay command should be as follows:
set_input_delay 4.5 -clock PHI1 {IN1}

Does the load-dependent delay of the driving cell equal the Clock to output of the L1 cell??

Thanks