I recommend inverters with each stage equally tapered.
I once hand-designed a clock tree using buffers which
had a 1:3 taper internally. There was a minor tplh/tphl
asymmetry. Along the many stages, this asymmetry
accumulated, as there was no cancelling inversion, to
the point that a 50/50 input clock ended up about 60/40
and I was all out of setup time (the whole reason of hand-
designing the clock tree, was to support hand-designed
logic that could run at a main clock 50% faster than the
standard cell library DFFs could self-toggle).
For logic that has a ton of timing slack you probably
do not care. But if you care about preserving duty
cycle or the width of one phase or the other, or are up
against the clock-Q-logic-D-clock cycle limit, you
may well need to take more care.