Inverters in clock path

[Raghu MS]

What happens if we use only inverters in the clock path instead of buffers?

 

[ThisIsNotSam]

You can build a clock tree with nand/xor gates if you want. It works. Inverters over buffers? No problems. The tools can make the logic be correct no matter what.
Now, there might be performance issues. Maybe the CTS has a higher load to drive and requires more routing resources, etc. The best thing to do is to check with the PDK/library what are the recommended cells to be used in the CTS.

 

[ranaya]

What happens if we use only inverters in the clock path instead of buffers?

Most of the cell libraries provide a dedicated inverters and buffers set for CTS. They're specific for this use since they provide balanced rise/fall transitions, typically named as CKINV*/CKBUF* in the libraries. I myself prefer CKINV* instead of CKBUF* aiming for lower CT power. In most of the CKBUF*s I have seen in libraries have quite larger transistors in the second stage (of 2 cascaded inverters) which is over killing for CT timing and area. It all depends on the properties of the cells in your .lib. You need to do an experiment to see what suits your need.

Anuradha

 

[dick_freebird]

I recommend inverters with each stage equally tapered.

I once hand-designed a clock tree using buffers which
had a 1:3 taper internally. There was a minor tplh/tphl
asymmetry. Along the many stages, this asymmetry
accumulated, as there was no cancelling inversion, to
the point that a 50/50 input clock ended up about 60/40
and I was all out of setup time (the whole reason of hand-
designing the clock tree, was to support hand-designed
logic that could run at a main clock 50% faster than the
standard cell library DFFs could self-toggle).

For logic that has a ton of timing slack you probably
do not care. But if you care about preserving duty
cycle or the width of one phase or the other, or are up
against the clock-Q-logic-D-clock cycle limit, you
may well need to take more care.