Hi again Keith,
thanks for your suggestions and time.
Well, Friday night, and since one hour I was checking what the problem could be (30 minutes more documenting the results here).
I read your hint about Kp and Gamma. That made me pay more attention to the parameters and I found the attached table (see attached table).
As we can see in this table:
GAMMA: Bulk threshold parameter = 632455 (for both pmos and nmos)
KAPPA: Saturation field factor = 0.01 V–1 (for both pmos and nmos)
that means for the PMOS and NMOS Gamma and Kappa are the same.
I hope you could read the last attachment where they explain that if Wn=Wp and Ln=Lp then the Ids Current for the NMOS is proportional to the mobility of the electrons and the Ids Current for the PMOS is proportional to the mobility of the holes, so:
Ids(nMOS) ~ Mn and Mn=0.068
Ids(pMOS) ~ Mp and Mp=0.025
this parameter is called in spice Carrier mobility, and is represented by Uo.
for that reason:
Ids(nMOS)/Ids(pMOS) ~ Mn/Mp = .068/0.025 = 2.72
which means that Ids(nMOS) is aprox. 2.72 times bigger Ids(pMOS)
that's why they do recommend to make Wp aprox. twice Wn (actually almost 3 times, 2.7), to compensate this current difference and to compensate switching discrepancies (switching from 0 to 1 should take approximately the same time as switching from 1 to 0).
So far so good, the problem was that the simulation was not showing the expected difference in the currents.
I just made a change in the models and now they look like this:
.model my_nmos nmos (level=3 uo=0.068 )
.model my_pmos pmos ( level=3 uo=0.025)
and now the simulation works fine.
attached you can see the screenshots. the schematic is the same, I only changed the model definition.
if I use Wn=Wp=1u and Ln=Lp=1u I can see that the Ids(nMOS)=4.7nA and Ids(pMOS)=1.73nA.
To compensate I am going to use Wp=2.72u, Wn=1u, Ln=Lp=1u and I get Ids(nMOS)=Ids(pMOS)=4.7nA
The demonstration is done: the difference is due to the different Carrier mobility parameter uo.
Thank you very much for your suggestions, they helped me to get to the solution of the problem.
Have a nice weekend!
---------- Post added at 22:21 ---------- Previous post was at 22:10 ----------
Thanks also to dick_freebird. Yes, indeed, then Kp is proportional to uo.
For my simulation it is enough if I define the model like this:
.model my_nmos nmos (level=3 uo=0.068 )
.model my_pmos pmos ( level=3 uo=0.025)
also as Keith mentioned "KP should be around 24u for NMOS and 8u for PMOS depending on the process" which is actually 24/8= 3 ~ 2.72
Have a nice weekend!
---------- Post added at 22:27 ---------- Previous post was at 22:21 ----------
I am a bit rusty at this, but hopefully someone will jump in with some proper device physics, but I think it is the KP that has a marked effect on the saturation current. KP should be around 24u for NMOS and 8u for PMOS depending on the process. I don't think u0 comes into the equation.
Keith.
---------- Post added at 20:00 ---------- Previous post was at 19:49 ----------
Also, I think a value for gamma would make sense - around 0.8 for NMOS and 0.4 for PMOS.
Keith.
from the table gamma is the same for nMOS and pMOS and actually:
GAMMA: Bulk threshold parameter = 0.4^0.5 = 0.632455 (for both pmos and nmos)
Exactly, Kp is proportional to the carrier mobility and 24(nmos) / 8(pmos) = 3 ~ 2.72 ( uo(nmos)/uo(pmos)=.068/0.025 = 2.72 )
Thank you!