Well, there has been a rule in Verilog saying don't use blocking and non-blocking statements in the same process. I believe the language LRM says it in a slightly different way. It says the order that blocking and non blocking statements get executed is undefined.
In order to use blocking statements to get the intermediate result, and then assign it to the register by non-blocking (like VHDL does), it assumes that blocking statements get executed first, followed by non-blocking statement. This is not guaranteed though, even if the blocking statements are placed in the code before non-blocking statements.