Yesterday I was interviewed @Intel. I got a question which I could not explain. Please help me with that :
Given a 256-input NAND gate how many test cases are required to verify it and how much coverage it will give ? Do we need to run all 2^256 cases to get 100% coverage.
Thank you very much for response. I understand that you are giving almost complete exercise to the design but can you tell me that what would be coverage ? and how would we get satisfied that the verification is done.