Interview Question for ASIC Design

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nandithaa_m

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Hi Guys,

I am preparing for an interview and can you provide me an answer for the following question ?

Why do designers avoid a clock with 0 rise time ?
 

I hope I understood your question correctly; I've got to say: because it's impossible to build a clock with rise time = 0.
So we have to consider the rise time effect on our design.
 

Hello,
Rise time means 0 to 1 transition, now question is how 0 to 1 transition occurs,for occurring,0 to 1 transition,these should pass through some logic...if is pass through some logic,thn it is not possible to do it with 0ns delay...so we need to consider rise time..and same for fall time..
 
To reduce also the clock feedthrough effect=> reduce errors
 

designers don't avoid it... zero transition is not possible to acheive so designers account for it.
 

Thanks for the responses. It helps.
 

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