1.For an fpga design what is the amount of the internal memory to be kept within in a module.
2.how to access this memory can it be like this
without clock
if(mem==23)
begin
end
or with respect to clock
FPGA has different memory implementation.
1. Synchronous memory using block RAM.
2. Asynchronous memoru using CLB
3. Memory using FF's
The code which u have written array with index. Normally synthesis tool will not infer memory for such type of code. u have to write a code in the specified pattern defined by the synthesis tool.
the code u have written will infer flip flops with decoding logic implemented in CLB's