internal clock generation

[vaf20]

hi all
i want to generate clock puls in FPGA or CPLD internally!
as u know i can use gate propagation dely to generate it like as following code
clk<= ~clk
but this can not be measured and exactly is not reliable because of changing some factors .
any comment or idea
tnx ahead

 

[ipcore]

It's for function simulation only,can't be use for generate clock

 

[jay_ec_engg]

I know many algorithms for generating internal clock...using DF and buffers and inverters... but frankly speaking.... its not at all good idea to generate internal clock.....its not at all reliable ....

 

[nyquist]

i agree, it's not a good idea: depending on the placing of inverters and routing of connections the period of a ring oscillator can change up to 50-60% on the same board. I suppose you don't want to use complicated PLL/DLL architectures to control the period

 

[gayu]

If internal clock generation is not appreciated, then why do we go for it in microprocessors.Why donot we generate a clock using optical signals externally and distibute it?