vaf20
Full Member level 3
hi all
i want to generate clock puls in FPGA or CPLD internally!
as u know i can use gate propagation dely to generate it like as following code
clk<= ~clk
but this can not be measured and exactly is not reliable because of changing some factors .
any comment or idea
tnx ahead
i want to generate clock puls in FPGA or CPLD internally!
as u know i can use gate propagation dely to generate it like as following code
clk<= ~clk
but this can not be measured and exactly is not reliable because of changing some factors .
any comment or idea
tnx ahead