fpga internal tristates
The datasheets used to list this feature, but it usually deeply buried. The reason is not many people care about the number of buffers as long as they never run out! In the Xilinx parts, these buffers and distributed within the fabric of the CLBs. On a regular grid, these elements will appear among the CLBs or Slices. With the Xilinx tool, you can always open FPGA Editor, locate a few of these blocks and quickly estimate the total since the placement pattern is fixed.
I would suggest coding up a quick test case and placing it in your part. Look at the reports, if you are critically low on T-Bufs, it should tell you or fail. After that, you just have to trust the tools to find a way to implement your logic. Usually, they are very good. I cannot remember having a fitting problem with the available T-Bufs for internal busses.
If you are still concerned, contact your local sales rep. They can query the factory and get an exact number for you.