interfacing two blocks where both transfer data in posedge

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dilan2005

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hi
i need to interface BLOCK ram (in spartan3E) with MII ethenet interface . as it seems to me the both ram and eth are operatord on positve clk edge . i obtain the clk from ethernet chip to drive the entire logic. it is obvious as i think data is not ready when MII reading from the data lines.



please show me the way. i really appreciate if the solution in verilog.
Thanks

dilan
 

Re: interfacing two blocks where both transfer data in posed

i do not know how your system work but i think the simplest way is to invert the clock and make the block ram operate at negative clock edge.
 

Re: interfacing two blocks where both transfer data in posed

Hi,

Your doubt is not clear to me. One thing I can say is you can delay the next stage clock by inversion.
 

Re: interfacing two blocks where both transfer data in posed

what do you mean by obtaining the clock. since ethernet is serial and i hope you are storing probably 32 bit data in RAM, are you dividing the clock and giving to the RAM.
 

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