Interfacing a memory card with AT89C52 for storing the code

[Help]

kiel code at89c52

Hi,

Yeah..i already can generate the Hex file. Thank you very much ya..

After i burn the hex and run on my testing board. After that i open XTALK, it show 1) PAULMON2 then i type 1. It show nothing.

May i know what's the next process?

I just change some in .asm file.

;.equ baud_const, 0      ;automatic baud rate detection
.equ  baud_const, 244   ;9600 baud w/ 22.1184 MHz

Thank you

 

[IanP]

paulmon2

I am not sure if XTALK will work for you ..
Better try HEPERTERMINAL ..
You should see something like this:

PAULMON2 Loc:8000 >

and after you press ? - for HELP:

PAULMON2 Loc:8000 >                   
Help

Standard Commands
  ?- This help list
  M- List programs
  R- Run program
  D- Download
  U- Upload
  N- New location
  J- Jump to memory location
  H- Hex dump external memory
  I- Hex dump internal memory
  E- Editing external ram
  C- Clear memory
User Installed Commands

PAULMON2 Loc:8000 >

or if you would like to see all what is going through the serial port you can use another terminal simulator ..
For example, the RFI INTERM .. see attached picture ..

Rgds,
IanP

 

[Help]

step at89c52 controller

Hi Ianp,

Sorry, I'm found some wiring connection problem on serial. I think now the testing board everything is fine and thank for intro the new serial diagnostic software to me, it is very nice and we can monitor the transmistion indication as well.

How to download hex file to SRAM? What does the sentence mean Begin ascii transfer of Intel hex file, or ESC to abort. This message is for D-Download command. What should we type after this sentence?

...during in monitor mode that runs under PAULMON2...

Using C52-EVB method. Can the Keil compiler link to C52-EVB board? Which mean when the Keil is Start Debug debuging the C code at the same time C52-EVB will start simulate the haarware as well. So, we can real time debuging the result. Is it possible?

Thank you.

 

[IanP]

functions of at89c52 programmer

How to download hex file to SRAM? What does the sentence mean Begin ascii transfer of Intel hex file, or ESC to abort. This message is for D-Download command. What should we type after this sentence?

Use HyperTerminal ..
After yo see "begin ascii transfer..." goto TRANSFER (see picture below) and select SEND TEXT FILE, then browse (All Files) and select file you would like to transfer .. try EX1 .. .txt.hex as an example, then hit OK and transfer should begin ..

Rgds,
IanP

PS1. The "ASCII Intel Hex" is any HEX file in the Intel format ..
PS2. I can't answer you questions with regard to KIEL - I've never used it ..

 

[Help]

sample program for flash write in at89c52

Hi Ianp,

I will test result later then feedback to you soon.

This few day while i doing the C51-EVB. Me also finding some new technology about how to expand the at89c52 CODE and DATA. Do you have any idea how to expand the program memory to more than 64KB for small MCU?

I have found some article discussing about the 8051 memory expanded. You can have a look..It describes how you can extend both the program and data memory without using additional pins for bank switching.
**broken link removed**
Do you know what's between 8051 and 512kB flash memory PME-51 logic IC they use? shown on Figure 3: PME-51 system diagram and how to control it?

Does anyone have any idea, please join in have a discussion. Thank you...

Bst Rgd,
Help

 

[Help]

28c64

Hi Ianp,

I have tested the C51-EVB. I already try to send the myPAULM2.hex and ex1_asm.txt txt file to SRAM there is no problem. But then..when using the hello.hex will be the error: 3218 bytes unable to write occur and i have tried compile to generate a new hello.hex file again then send to SRAM again but the result still the same...

May i know where is the problem?

Thank you.

 

[IanP]

at89s52 derivatives

If other hex files (in the INTEL-HEX format) can be downloaded I can’t see any reason why the HELLO.hex couldn’t be written into SRAM ..
Make sure it is definitely in the INTEL-HEX format ..
Before you try to download it again flash the PC’s serial port buffer by re-starting HyperTerminal ..
Some of these steps are described here:
https://www.pjrc.com/tech/8051/board5/first_use.html

Rgds,
IanP

 

[Help]

c code at89c52

Hi,

Ya, i already follow the step and i also have restart the Hyperterminal. It alway come out the same error. The hyperTerminal and the hex file have abit different. The hyper show
:078E560099.FDC299F5992274
but the hex file is
:078E560099FDC299F5992274
Is it anything wrong there?

Please can you try for me the hello.hex

Thank you.

 

[IanP]

hyperterminal to send data to at89c52

Please can you try for me the hello.hex

no probles, file transfers without errors ..

Try to do this:
In HyperTerminal Properties - ASCII setup, uncheck all booxes, no echo, nothing ..
Reset 89C52, restart Hyperterminal and try again ..

It is Intel-Hex-format file and transfer itself has nothing to do what's inside it ..

Rgds,
IanP

 

[Help]

fat16 mmc editor proteus

Hi Ianp,

I'm realize something actually the '.' dot is echo charactor. The hex file is ok. I have download the Banner Example Program file from https://www.pjrc.com/tech/8051/board2/construct.html there is 3 .obj file which is ex1_2, ex1_4 and ex1_8. I only can use ex1_8 to download with no error occur. Is it because my testing board c52 A15 is connected to SRAM /CE? So that the address is starting on 0x8000? Is it the ex1_8 is for addres 0x8000?

Do we need to do any configuration on compiler?

Thank you.

 

[IanP]

asm to hex 8952

The ex1_2.obj suppose to be loaded to 0x2000 (.org 2000h), ex1_4.obj (.org 4000h) to 0x4000 and ex1_8.obj to 0x8000 (.org 8000h) ..
If physical SRAM starts at 0x8000 you can’t download anything to addresses below 0x8000, but you can use address above 0x8000 ..

Looking at the KEIL’s page from your post - can’t help you much – I’m not KEIL user ..

Rgds,
IanP

 

[Help]

fat32 at89c52

Hi fren,

I already success to do the address configuration on KEIL's. I can display the \[Hello World 491 sin(1.491023) = 0.996820...\] on Hyperterminal already...Thank alot alot ya...feel very happy after success..

I have another question. If 32k code is still not enough for me. If I would like to using more than 64K of code space but i still like to use SRAM to store the code. Is it still able to do that? How can i do?

I have found one of the EPROM sample to store the CODE. (reference from THE FINAL WORD ON THE 8051)

Thank you

I would like to know is it if we able to download the Hex file to SRAM then we can run the CODE on SRAM?

If YES, then we send the hex file from hyperterminal to MCU then the MCU have to do some Hex convertion. After do the convertion then send it to SRAM, am i rite?
Like the RAM data picture show bellow..

Thank you.

 

[IanP]

at89c52 con ram externa

Using bank switching (and some extra ‘logic’ to combine PSEN, RD, WR and one available pin, for example, P1.7) it’s possible to connect two 64Kb memory banks (BANK1 and BANK2) to contain code memory giving a total of 128Kb ..

Also, it is possible to use a 128Kb SRAM chip (as BANK2 in the above example) and take A16 address line from another P1-pin, for example, P1.0 ..
After power up or reset P1.0 is set to ‘1’, thus access is to the upper 64Kb, that is page 1 ..
Therefore any program which is to be executed from this memory upon power up should be uploaded into PAGE 1 – upper 64Kb (PAGE 0 – lower 64Kb can be accessed when P1.0 is cleared to ‘0’) ..

So, there are several options here but PaulMon2 (without major modifications) is just not suitable for this purpose ..

However, I'm curious as to the reasoning behind implementing bank switching (‘old’ approach) rather than to switch to a processor with a larger address space?

Rgds,
IanP

 

[Help]

base datos at89c52

Hi Ianp,

Very much thank your for your reply. I'm worry no one will help me agian.

Using bank switching (and some extra ‘logic’ to combine PSEN, RD, WR and one available pin, for example, P1.7) it’s possible to connect two 64Kb memory banks (BANK1 and BANK2) to contain code memory giving a total of 128Kb ..

I can't get 64Kb SRAM in my city . So, temporary that's the only way to use 32Kb to design. May be i will ask someone to order for me. I think from your explanation the P1.7 is for memory paging. For using 32Kb memory, i have using P1.0 and P1.1 for memory paging.

Also, it is possible to use a 128Kb SRAM chip (as BANK2 in the above example) and take A16 address line from another P1-pin, for example, P1.0 ..
After power up or reset P1.0 is set to ‘1’, thus access is to the upper 64Kb, that is page 1 ..

For this concern, When initialize power up the P1.0 and P1.1 will set to '1' to select U3 as PAGE1. I'm not sure is it correct not?

However, I'm curious as to the reasoning behind implementing bank switching (‘old’ approach) rather than to switch to a processor with a larger address space?

Actually i more like to use new technology or new method to do so..I'm get used to it on 8051/52. I'm not sure whether got any target is more then >64kB. I think temporary using small MCU for my hobby and easy for me to source the MCU and burner in my city.

Bellow is the circuit. I'm not sure wheter this circuit is able to read/write the CODE and DATA not. If i would like to use 1st 3 SRAM for CODE and the last one is for DATA, how am i to control it?

Another question, what should i start now? Currently i'm writing the ASCII to Hex code and use the serial send the data to SRAM. Is it this the part i need to do?

Please guide me...

Thank you

 

[IanP]

what is data rates of at89c52

First of all, if you want to use all addresses from 0x0000 to 0xFFFF, ‘banking’ concept does not allow you to keep MONITOR program inside the 89C52 – PaulMOn2 does not support this address range at all ..
It (MONITOR) has to be moved to the external code memory BANK (you called it PAGE) ..
My suggestion is that you go for one 64Kb EPROM/FLASH [BANK1] and 128Kb SRAM (eg. CY62128LL – 128Kx8)[BANK2] as program memories, where BANK2 can have two 64Kb pages and it can also be used as DATA memory ..
In addition, there are 4 memory-mapped devices such as 32/64Kb DATA memory or I/O port(s) ..
After all, 64Kb(128Kb) in the 8051-world is ‘plenty’ ..
So, have a look at the attached diagram - do you like this concept?

Rgds,
IanP

 

[Help]

circuit to interface mmc card with at89s52

Hi,

where BANK2 can have two 64Kb pages and it can also be used as DATA memory ..
In addition, there are 4 memory-mapped devices such as 32/64Kb DATA memory or I/O port(s) ..

Do you mean half of the BANK2 memory is use for CODE and another half is for DATA memory and also can be I/O port's?

The attached diagram i'm not so understand. Please can you give some explanation..
- Is it there have 2 jumper (STARTUP BANK SELECT) to set?
- From this diagram, there is 3 control pin (P1.4, P1.5, P1.6). The P1.6 is bank select. May i know if the program is running the CODE on BANK2 but one of the function calling the DATA from BANK1. How the P1.6 do the switching? Is it the P1.6 will select BANK1 and store the DATA to internal MCU RAM then switch it back to BANK2 CODE then call the DATA back from internal RAM? Sorry, feel abit blur

Just now i was go town find the SRAM for 64K and 128K. They don't have sell this IC. If using EPROM, i don't have the burner.. Feel like very difficult for me.. Temporary, is it possible we start on 32Kb SRAM? I think after i get the concept already then i will know how to use EPROM and i think EPROM have to use UV to erase the CODE will take sometime to erase also.

I think i have already finished the convertion part using serial receive the ASCII code then convert the data to Intel-Hex but haven't know how to download to SRAM.
Is it all the data that we convert have to download to SRAM start from 0x0000, so the 0x0000 address will store the after following RECTYPE Intel-Hex data, am i rite?

Thank you.

 

[IanP]

interfacing mmc to at89c52 using c program

Temporary, is it possible we start on 32Kb SRAM?

Yes, why not ..

Have a look at the attached drawings ..
They give you more details on how the bank swiching may be realized in hardware ..
It really does not matter which P1.X are used; the MONITOR program has to use them and when you write your code you have to use them, too ..

How the P1.6 do the switching?

Somewhere at the end of the code in BANK0:

; Switch to BANK1
			ORG		0FFFBh
Switch_Bank_1:		CLR		P1.6

and to switch back to BANK1 from BANK0, at the end of the code in BANK1:

; Switch to BANK0, BANK1 = 32Kb
			ORG		07FFBh
Switch_Bank_0:		SETB		P1.6

and in the both cases the micro will fetch the next instruction from the other memory BANK ..


So, once again, have a look at the attached pictures ..

Rgds,
IanP

 

[Help]

power on reset circuit for at89c52

Hi,

Q1:The Bank Switching picture. The 74LS139 Select A address A0, it should be connected to Select B A0 rite?
Q2: What is the function for Exp RD and Exp WR on 74LS139?
Q3: Memory Banks picture. The BANK0 is it a ROM? Why the A14/A15 is on the same pin? and How come the A14 have 2 pin on one IC? It share with the A14//WE? and Why need jumper for A14/A15 and A14//WE?

I already drawn out the circuit. If the circuit is correct mean that i already understand your previous explanation. Please have a look..

Thank you.

 

[IanP]

c51-mmc.zip download

I hope this set of drawings will clarify some of your questions ..

The BANK0 is it a ROM? Why the A14/A15 is on the same pin? and How come the A14 have 2 pin on one IC? It share with the A14//WE? and Why need jumper for A14/A15 and A14//WE?

Someone whod designed this circuit wanted to make it as flexible as possible (at least for the time when it was designed) ..
Jumpers allow you to use differt memory chips; for example, in BANK0 you can use 27C64, 27C128, 27C256, 27C512, 28C64, 28C256 and 62256, in BANK1 62256(32Kb-28pin) or 20100(128Kb-32pin) and some EPROMs incl. 27C512, 27C256 and so on ..
Check out pin configuration, specially A14 and A15, to see why ..
If you don't intend to use those chips - don't worry about A14 and jumpers ..

Rgds,
IanP

 

[Help]

at89s52 read byte c code

Hi,

I reallize something from the schematic. May i know why don't we control the SRAM using /CE instead of using BANK /WR and BANK /RD? If using /WR /RD to control will used more hardware logic compare with /CE.. Is there any reason?

I re-draw again the circuit. Please have a look..

Thank alot...

(abit hard to get the memory ic here.. I think have order from Farnell or RS then can )