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integrator saturation problem

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finerain22

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I am a new comer to Sigma-Delta Modulator.
Now I working on a two order SDM, ENOB=13bit
Fist I do ideal simulation in Matlab, and find the output swing of integrator is -3v~+3v

But 3.3v transistors are used in our design, does this means the design in Matlab is improper, I have to choose a another set of coefficients?

Another question, in the textbook Intorductio to Sigma-Delta Modulators(Schreier), there is a chaper discribs example circuits. The author said on the book, due to the simulation in Matlab only use one as unit, the designer to do some conversion from unitless form to real voltage. Does this scaling or denormalization will effect the integrator output swing? and why?
 

finerain22

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After voltage scalling, the output swing of integrator in SDM using verilog-a model is different from the SDM model using Matlab model, how would this happen?
 

ShaunZ

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finerain22 said:
After voltage scalling, the output swing of integrator in SDM using verilog-a model is different from the SDM model using Matlab model, how would this happen?
That depends on your verilog-a model. Most op-amp models take nonideal factors such as saturation, offset, etc into consideration, while matlab models concern math issue only.
 

finerain22

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ShaunZ said:
finerain22 said:
After voltage scalling, the output swing of integrator in SDM using verilog-a model is different from the SDM model using Matlab model, how would this happen?
That depends on your verilog-a model. Most op-amp models take nonideal factors such as saturation, offset, etc into consideration, while matlab models concern math issue only.
In the verilog-a model, use voltage-control-voltage source to model the opamp, the gain is 2000, offset and saturation are not concerned.
The simulation time is long, due the accumalted error is so large, that the verilog-a model shows a diffence from the matlab model.
This maybe the point.
Thanks for your reply.
 

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