Integrating blocks in Power management Layout

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msm_aravind

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power manage layout

Hi,

Can anyone comment on the minimum spacing requirement between Bandgap reference module layout and DCDC regulators(w.r.t.switching node)module layout in 65um technology to minimize the transmission of noise generated by DCDC ?PowerFETS inside DCDC are well surrounded by double guard rings.It is inside a power management IP used in a SoC .

thanks,
aravind
 

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