Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

instantiation of EDIF file in ActiveHDL

Thread starter blackhawk155
Start date Jan 1, 2012

Status: Not open for further replies.

Jan 1, 2012

#1

B

blackhawk155

Newbie level 4

Hi, I wanna know how to make an instance of edif file in VHDL with ActiveHDL and use it in my code ?

Jan 1, 2012

#2

gck

Full Member level 3

hey,
Check out this article,
MANUAL: Active-HDL 9.1 Software Manual - Using EDIF Netlists with Active-HDL (11/2/2011)

Status: Not open for further replies.

Similar threads

M
How to instantiate another vhd file inside testbench, where the testbench is used for opening files
- Started by metamisers
- Jan 6, 2024
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
A
instantiation error in Xilinx IP CORE
- Started by Andreh12
- Jun 11, 2022
- Replies: 7
PLD, SPLD, GAL, CPLD, FPGA Design
VHDL Testbench §§ Instantiation of entities
- Started by Ilnheim
- Apr 2, 2022
- Replies: 7
PLD, SPLD, GAL, CPLD, FPGA Design
R
problem of fpga
- Started by rllv24
- Mar 24, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
K
What's the difference between RAM and ROM with a coe files in Xilinx FPGA?
- Started by kevinwang65
- Mar 11, 2024
- Replies: 13
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top